Recommended PCB layout understanding - ADM2572 datasheet The Next CEO of Stack OverflowCompeting PCB Crystal layout recommendationsPCB layout of buck converter: capacitor placementDetails on PCB layout for microcontrollerConnecting grounds of DC-DC converter at one point2 Layer RF PCB With Chip AntennaGND plane and vias on a two layer PCBGrounding and Signal Integrity of my PCB Layout (ADC, SMPS, SD card, USB)PCB layout buck converterRouting traces over traces in two layer pcb
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Recommended PCB layout understanding - ADM2572 datasheet
The Next CEO of Stack OverflowCompeting PCB Crystal layout recommendationsPCB layout of buck converter: capacitor placementDetails on PCB layout for microcontrollerConnecting grounds of DC-DC converter at one point2 Layer RF PCB With Chip AntennaGND plane and vias on a two layer PCBGrounding and Signal Integrity of my PCB Layout (ADC, SMPS, SD card, USB)PCB layout buck converterRouting traces over traces in two layer pcb
$begingroup$
I have problem with understanding and applying this recommended PCB layout to my design (image from datasheet, page 18):
This is isolated RS485 transceiver with integrated isolated high frequency DC-DC converter (200MHz?).
There is a trace connecting pin 11 and pin 14 that crosses the other trace. How should I do this crossing on PCB? Should I create this connection on second layer?
pcb documentation
asked Mar 22 at 11:52
KamilKamil
4,50062752
$endgroup$
add a comment |
$begingroup$
I have problem with understanding and applying this recommended PCB layout to my design (image from datasheet, page 18):
This is isolated RS485 transceiver with integrated isolated high frequency DC-DC converter (200MHz?).
There is a trace connecting pin 11 and pin 14 that crosses the other trace. How should I do this crossing on PCB? Should I create this connection on second layer?
pcb documentation
asked Mar 22 at 11:52
KamilKamil
4,50062752
$endgroup$
1
$begingroup$
Analog picked a really poor image to use. I figure it started out in color, with the layers represented by different colors. That would show how to route it. I expect the image got converted to black and white, and the reviewers didn't notice the difference.
$endgroup$
– JRE
Mar 22 at 12:26
add a comment |
$begingroup$
I have problem with understanding and applying this recommended PCB layout to my design (image from datasheet, page 18):
This is isolated RS485 transceiver with integrated isolated high frequency DC-DC converter (200MHz?).
There is a trace connecting pin 11 and pin 14 that crosses the other trace. How should I do this crossing on PCB? Should I create this connection on second layer?
pcb documentation
asked Mar 22 at 11:52
KamilKamil
4,50062752
$endgroup$
I have problem with understanding and applying this recommended PCB layout to my design (image from datasheet, page 18):
This is isolated RS485 transceiver with integrated isolated high frequency DC-DC converter (200MHz?).
There is a trace connecting pin 11 and pin 14 that crosses the other trace. How should I do this crossing on PCB? Should I create this connection on second layer?
pcb documentation
pcb documentation
asked Mar 22 at 11:52
KamilKamil
4,50062752
asked Mar 22 at 11:52
KamilKamil
4,50062752
asked Mar 22 at 11:52
KamilKamil
4,50062752
asked Mar 22 at 11:52
KamilKamil
4,50062752
asked Mar 22 at 11:52
KamilKamil
4,50062752
4,50062752
1
$begingroup$
Analog picked a really poor image to use. I figure it started out in color, with the layers represented by different colors. That would show how to route it. I expect the image got converted to black and white, and the reviewers didn't notice the difference.
$endgroup$
– JRE
Mar 22 at 12:26
add a comment |
1
$begingroup$
Analog picked a really poor image to use. I figure it started out in color, with the layers represented by different colors. That would show how to route it. I expect the image got converted to black and white, and the reviewers didn't notice the difference.
$endgroup$
– JRE
Mar 22 at 12:26
1
1
$begingroup$
Analog picked a really poor image to use. I figure it started out in color, with the layers represented by different colors. That would show how to route it. I expect the image got converted to black and white, and the reviewers didn't notice the difference.
$endgroup$
– JRE
Mar 22 at 12:26
$begingroup$
Analog picked a really poor image to use. I figure it started out in color, with the layers represented by different colors. That would show how to route it. I expect the image got converted to black and white, and the reviewers didn't notice the difference.
$endgroup$
– JRE
Mar 22 at 12:26
add a comment |
3 Answers
3
active
oldest
votes
$begingroup$
The text in the PCB layout section implies that you should be using either a two or four layer board - it includes tips for improving EMI, and some of them depend on whether you are using a two or four layer board.
It also directs you to have a "keep out" area for the ground plane under L1 and L2. This is the same area where C1 and pins 11 and 14 are.
It also says:
Ensure that GND2 (Pin 14) connects to GND2 (Pin 11) on the inside (device side) of the C1 100 nF capacitor.
All of that leads me to conclude that you will have to run the connection of pin 11 and pin 14 on the ground plane layer.
There's just no other place for it that fits.
The application notes for the adm2582e shows a completed layout.
The trace connecting pins 11 and 14 (red trace) is indeed on the other side of the board from C1 (green traces:)
C1 is the 100nF capacitor in the lower right corner by the two ferrite beads. Pin 11 is the lower right pin of the IC.
Sometimes the datasheet isn't enough. Often times you can find application notes that help a lot with actually using the parts.
Failing that, a look at evaluation boards (and their documentation) can show you what the datasheet really meant.
answered Mar 22 at 12:18
JREJRE
22.5k53773
$endgroup$
add a comment |
$begingroup$
Yes you need to put that trace on another layer.
To confirm this, just look at the evaluation kit layout made by Analog Devices
The photos show quite clearly that track on a different layer:
https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADM2582E.html#eb-overview
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
$endgroup$
add a comment |
$begingroup$
If you don't want to change layers, you can run the trace under the device (so long as you maintain your separations due to voltages)
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
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3 Answers
3
active
oldest
votes
3 Answers
3
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
The text in the PCB layout section implies that you should be using either a two or four layer board - it includes tips for improving EMI, and some of them depend on whether you are using a two or four layer board.
It also directs you to have a "keep out" area for the ground plane under L1 and L2. This is the same area where C1 and pins 11 and 14 are.
It also says:
Ensure that GND2 (Pin 14) connects to GND2 (Pin 11) on the inside (device side) of the C1 100 nF capacitor.
All of that leads me to conclude that you will have to run the connection of pin 11 and pin 14 on the ground plane layer.
There's just no other place for it that fits.
The application notes for the adm2582e shows a completed layout.
The trace connecting pins 11 and 14 (red trace) is indeed on the other side of the board from C1 (green traces:)
C1 is the 100nF capacitor in the lower right corner by the two ferrite beads. Pin 11 is the lower right pin of the IC.
Sometimes the datasheet isn't enough. Often times you can find application notes that help a lot with actually using the parts.
Failing that, a look at evaluation boards (and their documentation) can show you what the datasheet really meant.
answered Mar 22 at 12:18
JREJRE
22.5k53773
$endgroup$
add a comment |
$begingroup$
The text in the PCB layout section implies that you should be using either a two or four layer board - it includes tips for improving EMI, and some of them depend on whether you are using a two or four layer board.
It also directs you to have a "keep out" area for the ground plane under L1 and L2. This is the same area where C1 and pins 11 and 14 are.
It also says:
Ensure that GND2 (Pin 14) connects to GND2 (Pin 11) on the inside (device side) of the C1 100 nF capacitor.
All of that leads me to conclude that you will have to run the connection of pin 11 and pin 14 on the ground plane layer.
There's just no other place for it that fits.
The application notes for the adm2582e shows a completed layout.
The trace connecting pins 11 and 14 (red trace) is indeed on the other side of the board from C1 (green traces:)
C1 is the 100nF capacitor in the lower right corner by the two ferrite beads. Pin 11 is the lower right pin of the IC.
Sometimes the datasheet isn't enough. Often times you can find application notes that help a lot with actually using the parts.
Failing that, a look at evaluation boards (and their documentation) can show you what the datasheet really meant.
answered Mar 22 at 12:18
JREJRE
22.5k53773
$endgroup$
add a comment |
$begingroup$
The text in the PCB layout section implies that you should be using either a two or four layer board - it includes tips for improving EMI, and some of them depend on whether you are using a two or four layer board.
It also directs you to have a "keep out" area for the ground plane under L1 and L2. This is the same area where C1 and pins 11 and 14 are.
It also says:
Ensure that GND2 (Pin 14) connects to GND2 (Pin 11) on the inside (device side) of the C1 100 nF capacitor.
All of that leads me to conclude that you will have to run the connection of pin 11 and pin 14 on the ground plane layer.
There's just no other place for it that fits.
The application notes for the adm2582e shows a completed layout.
The trace connecting pins 11 and 14 (red trace) is indeed on the other side of the board from C1 (green traces:)
C1 is the 100nF capacitor in the lower right corner by the two ferrite beads. Pin 11 is the lower right pin of the IC.
Sometimes the datasheet isn't enough. Often times you can find application notes that help a lot with actually using the parts.
Failing that, a look at evaluation boards (and their documentation) can show you what the datasheet really meant.
answered Mar 22 at 12:18
JREJRE
22.5k53773
$endgroup$
The text in the PCB layout section implies that you should be using either a two or four layer board - it includes tips for improving EMI, and some of them depend on whether you are using a two or four layer board.
It also directs you to have a "keep out" area for the ground plane under L1 and L2. This is the same area where C1 and pins 11 and 14 are.
It also says:
Ensure that GND2 (Pin 14) connects to GND2 (Pin 11) on the inside (device side) of the C1 100 nF capacitor.
All of that leads me to conclude that you will have to run the connection of pin 11 and pin 14 on the ground plane layer.
There's just no other place for it that fits.
The application notes for the adm2582e shows a completed layout.
The trace connecting pins 11 and 14 (red trace) is indeed on the other side of the board from C1 (green traces:)
C1 is the 100nF capacitor in the lower right corner by the two ferrite beads. Pin 11 is the lower right pin of the IC.
Sometimes the datasheet isn't enough. Often times you can find application notes that help a lot with actually using the parts.
Failing that, a look at evaluation boards (and their documentation) can show you what the datasheet really meant.
answered Mar 22 at 12:18
JREJRE
22.5k53773
edited Mar 22 at 12:53
answered Mar 22 at 12:18
JREJRE
22.5k53773
answered Mar 22 at 12:18
JREJRE
22.5k53773
answered Mar 22 at 12:18
JREJRE
22.5k53773
22.5k53773
add a comment |
add a comment |
$begingroup$
Yes you need to put that trace on another layer.
To confirm this, just look at the evaluation kit layout made by Analog Devices
The photos show quite clearly that track on a different layer:
https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADM2582E.html#eb-overview
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
$endgroup$
add a comment |
$begingroup$
Yes you need to put that trace on another layer.
To confirm this, just look at the evaluation kit layout made by Analog Devices
The photos show quite clearly that track on a different layer:
https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADM2582E.html#eb-overview
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
$endgroup$
add a comment |
$begingroup$
Yes you need to put that trace on another layer.
To confirm this, just look at the evaluation kit layout made by Analog Devices
The photos show quite clearly that track on a different layer:
https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADM2582E.html#eb-overview
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
$endgroup$
Yes you need to put that trace on another layer.
To confirm this, just look at the evaluation kit layout made by Analog Devices
The photos show quite clearly that track on a different layer:
https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADM2582E.html#eb-overview
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
answered Mar 22 at 12:03
ElmesitoElmesito
1,974310
1,974310
add a comment |
add a comment |
$begingroup$
If you don't want to change layers, you can run the trace under the device (so long as you maintain your separations due to voltages)
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
$begingroup$
If you don't want to change layers, you can run the trace under the device (so long as you maintain your separations due to voltages)
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
$begingroup$
If you don't want to change layers, you can run the trace under the device (so long as you maintain your separations due to voltages)
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
If you don't want to change layers, you can run the trace under the device (so long as you maintain your separations due to voltages)
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
answered Mar 22 at 17:19
Stephen HewitsonStephen Hewitson
1
1
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
New contributor
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Stephen Hewitson is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
add a comment |
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$begingroup$
Analog picked a really poor image to use. I figure it started out in color, with the layers represented by different colors. That would show how to route it. I expect the image got converted to black and white, and the reviewers didn't notice the difference.
$endgroup$
– JRE
Mar 22 at 12:26