Can an x86 CPU running in real mode be considered to be basically an 8086 CPU?The start of x86: Intel 8080 vs Intel 8086?How do you put a 286 in Protected Mode?How do accelerators and CPU cards work on the Apple II?How to use the “darker” CGA palette using x86 Assembly?Examples of operating systems using hardware task switching of x86 CPUsDid the 286 go out of its way to follow the 8088 bus protocol?How did people program for Consoles with multiple CPUs?
Does a large simulator bay have standard public address announcements?
Why didn't the Space Shuttle bounce back into space as many times as possible so as to lose a lot of kinetic energy up there?
All ASCII characters with a given bit count
Why must Chinese maps be obfuscated?
Mistake in years of experience in resume?
Can I criticise the more senior developers around me for not writing clean code?
can anyone help me with this awful query plan?
basic difference between canonical isomorphism and isomorphims
Farming on the moon
Is it idiomatic to construct against `this`
How come there are so many candidates for the 2020 Democratic party presidential nomination?
Which big number is bigger?
Pre-plastic human skin alternative
Why does nature favour the Laplacian?
"The cow" OR "a cow" OR "cows" in this context
Retract an already submitted recommendation letter (written for an undergrad student)
Solving a quadratic equation by completing the square
Don’t seats that recline flat defeat the purpose of having seatbelts?
Finding a pattern, I'm stuck
Why did C use the -> operator instead of reusing the . operator?
How can Republicans who favour free markets, consistently express anger when they don't like the outcome of that choice?
How to limit Drive Letters Windows assigns to new removable USB drives
How could Tony Stark make this in Endgame?
What causes platform events to fail to be published and should I cater for failed platform event creations?
Can an x86 CPU running in real mode be considered to be basically an 8086 CPU?
The start of x86: Intel 8080 vs Intel 8086?How do you put a 286 in Protected Mode?How do accelerators and CPU cards work on the Apple II?How to use the “darker” CGA palette using x86 Assembly?Examples of operating systems using hardware task switching of x86 CPUsDid the 286 go out of its way to follow the 8088 bus protocol?How did people program for Consoles with multiple CPUs?
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)? Or are there differences between the two?
cpu x86
add a comment |
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)? Or are there differences between the two?
cpu x86
add a comment |
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)? Or are there differences between the two?
cpu x86
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)? Or are there differences between the two?
cpu x86
cpu x86
edited Apr 5 at 21:26
Stephen Kitt
41.5k8170178
41.5k8170178
asked Apr 5 at 20:45
user12245user12245
16123
16123
add a comment |
add a comment |
2 Answers
2
active
oldest
votes
An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example:
- newer CPUs run faster (in general);
- newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode);
- 286 and later CPUs add more address lines, and the wrapping behaviour of the 8086 meant that IBM had to add the infamous A20 gate to preserve backward-compatibility;
- instruction timing — the speed of individual CPU instructions — varies from one family to another; some instructions run more slowly on newer CPUs;
- implementation details vary, and in some cases, can affect run-time behaviour — for example, varying prefetch queue lengths mean that self-modifying code may not work on CPUs other than the model it was written for;
- some instructions behave differently — for example,
PUSH SP
on an 8086 decrementsSP
before pushing it, whereas on a 286 it decrementsSP
after pushing it, so the value on the stack is different; - bus interactions (
LOCK
prefixes) behave differently on the 8086/8088 compared to all later CPUs; - illegal opcodes which run without error on the 8086 produce exceptions on later CPUs;
- the 8086 has no instruction length limit, whereas instructions which are too long will produce exceptions on later CPUs;
- segment wraparounds inside an instruction or word access work on the 8086 but trap on later CPUs;
- stack wraparounds work on the 8086 but will shut down a 286 or later;
- divide errors behave differently on the 8086/8088 compared to all later CPUs.
The 8086 also has a few bugs which were fixed in later CPUs, but that generally doesn’t matter — all it means is that the workarounds which were needed on 8086/8088 are no longer necessary on later CPUs. (One example is the handling of interrupted instructions with multiple prefixes.)
Software which is actually affected by differences other than speed is very rare indeed, and you can count on the vast majority of software still technically working on a modern x86 CPU in real mode. Speed is another matter; famously, programs written using Turbo Pascal fail with an “Error 200” on CPUs faster than a 200MHz Pentium, and many games don’t cope well with faster CPUs (but some CPUs can be slowed down in creative ways).
Great write up, except speed issues are not really due a changed/extended ISA - they would occure as well back then when speed up occured - after all, having a 10 MHz 8086 was already in the early 1980s a way to screw programs made for a 4.77 MHz 8088
– Raffzahn
Apr 5 at 21:13
The fact that it applies to 8MHz v. 4.77 MHz 8086s doesn’t mean it stops applying when comparing any other CPU to an 8086/8088 ;-).
– Stephen Kitt
Apr 5 at 21:15
2
Another difference between the 8086 and chips with protected mode: the 286+ didn't wrap around addresses at the 1MB mark in real mode, so IBM had to add an A20 line mask to work around that issue: although not generally an issue on PCs, it could theoretically happen if the A20 line has been enabled to access the UMB region and a program tried using wraparound to access low memory. It's pretty unlikely however: I've never seen a program crash in that manner!
– ErikF
Apr 5 at 23:00
3
@ErikF: ugh, A20 is an issue on modern PCs for everything except running legacy code, if you boot in legacy BIOS mode. But even that whole way of booting is obsoleted by UEFI, but that doesn't stop the majority of Stack Overflow "osdev" / "bootloader" questions being about legacy BIOS boot sectors. (Which start in real mode with A20 disabled, so it has to be manually enabled if you want to use odd 1MB regions of memory.) Of course, Intel themselves continue to support the undocumented 8086 SALC instruction in 32-bit mode... agner.org/optimize/blog/read.php?i=25
– Peter Cordes
Apr 6 at 3:29
1
Thanks @ErikF, that was indeed an issue (minor nitpick: accessing UMBs didn’t require A20 control, only the HMA did). Significant effort went into correctly handling the A20 line in memory managers...
– Stephen Kitt
Apr 6 at 17:05
|
show 3 more comments
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)?
As so often it depends on your value of 'basically' (and there is no user visible difference between 8086 and 8088 beside speed).
Or are there differences between the two?
Well, it's so far the same, as every (modern) x86 operating in real mode will execute pure 8086 programs (*1) adhering to what were legal (*2) instructions (*3) on the 8086.
At the same time they are able to execute later extensions as well while in real mode. So it is possible to write 32-bit real mode programs, or use additional registers and instructions in real mode.
So a x86 isn't the same but for most parts (and depending on the CPU used) a compatible superset of an 8086.
*1 - Lets ignore 'external' hardware differences for this.
*2 - There are a few instructions that changed over time, including basic 8086 ones. They may cause incompatibilities in rare circumstances.
*3 - There are some non-instruction combinations (i.e. prefixes) that were ignored on 8086 but will throw interrupts on later CPUs or result in addressing errors. This is a classic case of later restrictions on less well defined behaviour (like double segment prefix and the like).
add a comment |
Your Answer
StackExchange.ready(function()
var channelOptions =
tags: "".split(" "),
id: "648"
;
initTagRenderer("".split(" "), "".split(" "), channelOptions);
StackExchange.using("externalEditor", function()
// Have to fire editor after snippets, if snippets enabled
if (StackExchange.settings.snippets.snippetsEnabled)
StackExchange.using("snippets", function()
createEditor();
);
else
createEditor();
);
function createEditor()
StackExchange.prepareEditor(
heartbeatType: 'answer',
autoActivateHeartbeat: false,
convertImagesToLinks: false,
noModals: true,
showLowRepImageUploadWarning: true,
reputationToPostImages: null,
bindNavPrevention: true,
postfix: "",
imageUploader:
brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/3.0/"u003ecc by-sa 3.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
allowUrls: true
,
noCode: true, onDemand: true,
discardSelector: ".discard-answer"
,immediatelyShowMarkdownHelp:true
);
);
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
StackExchange.ready(
function ()
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fretrocomputing.stackexchange.com%2fquestions%2f9588%2fcan-an-x86-cpu-running-in-real-mode-be-considered-to-be-basically-an-8086-cpu%23new-answer', 'question_page');
);
Post as a guest
Required, but never shown
2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example:
- newer CPUs run faster (in general);
- newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode);
- 286 and later CPUs add more address lines, and the wrapping behaviour of the 8086 meant that IBM had to add the infamous A20 gate to preserve backward-compatibility;
- instruction timing — the speed of individual CPU instructions — varies from one family to another; some instructions run more slowly on newer CPUs;
- implementation details vary, and in some cases, can affect run-time behaviour — for example, varying prefetch queue lengths mean that self-modifying code may not work on CPUs other than the model it was written for;
- some instructions behave differently — for example,
PUSH SP
on an 8086 decrementsSP
before pushing it, whereas on a 286 it decrementsSP
after pushing it, so the value on the stack is different; - bus interactions (
LOCK
prefixes) behave differently on the 8086/8088 compared to all later CPUs; - illegal opcodes which run without error on the 8086 produce exceptions on later CPUs;
- the 8086 has no instruction length limit, whereas instructions which are too long will produce exceptions on later CPUs;
- segment wraparounds inside an instruction or word access work on the 8086 but trap on later CPUs;
- stack wraparounds work on the 8086 but will shut down a 286 or later;
- divide errors behave differently on the 8086/8088 compared to all later CPUs.
The 8086 also has a few bugs which were fixed in later CPUs, but that generally doesn’t matter — all it means is that the workarounds which were needed on 8086/8088 are no longer necessary on later CPUs. (One example is the handling of interrupted instructions with multiple prefixes.)
Software which is actually affected by differences other than speed is very rare indeed, and you can count on the vast majority of software still technically working on a modern x86 CPU in real mode. Speed is another matter; famously, programs written using Turbo Pascal fail with an “Error 200” on CPUs faster than a 200MHz Pentium, and many games don’t cope well with faster CPUs (but some CPUs can be slowed down in creative ways).
Great write up, except speed issues are not really due a changed/extended ISA - they would occure as well back then when speed up occured - after all, having a 10 MHz 8086 was already in the early 1980s a way to screw programs made for a 4.77 MHz 8088
– Raffzahn
Apr 5 at 21:13
The fact that it applies to 8MHz v. 4.77 MHz 8086s doesn’t mean it stops applying when comparing any other CPU to an 8086/8088 ;-).
– Stephen Kitt
Apr 5 at 21:15
2
Another difference between the 8086 and chips with protected mode: the 286+ didn't wrap around addresses at the 1MB mark in real mode, so IBM had to add an A20 line mask to work around that issue: although not generally an issue on PCs, it could theoretically happen if the A20 line has been enabled to access the UMB region and a program tried using wraparound to access low memory. It's pretty unlikely however: I've never seen a program crash in that manner!
– ErikF
Apr 5 at 23:00
3
@ErikF: ugh, A20 is an issue on modern PCs for everything except running legacy code, if you boot in legacy BIOS mode. But even that whole way of booting is obsoleted by UEFI, but that doesn't stop the majority of Stack Overflow "osdev" / "bootloader" questions being about legacy BIOS boot sectors. (Which start in real mode with A20 disabled, so it has to be manually enabled if you want to use odd 1MB regions of memory.) Of course, Intel themselves continue to support the undocumented 8086 SALC instruction in 32-bit mode... agner.org/optimize/blog/read.php?i=25
– Peter Cordes
Apr 6 at 3:29
1
Thanks @ErikF, that was indeed an issue (minor nitpick: accessing UMBs didn’t require A20 control, only the HMA did). Significant effort went into correctly handling the A20 line in memory managers...
– Stephen Kitt
Apr 6 at 17:05
|
show 3 more comments
An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example:
- newer CPUs run faster (in general);
- newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode);
- 286 and later CPUs add more address lines, and the wrapping behaviour of the 8086 meant that IBM had to add the infamous A20 gate to preserve backward-compatibility;
- instruction timing — the speed of individual CPU instructions — varies from one family to another; some instructions run more slowly on newer CPUs;
- implementation details vary, and in some cases, can affect run-time behaviour — for example, varying prefetch queue lengths mean that self-modifying code may not work on CPUs other than the model it was written for;
- some instructions behave differently — for example,
PUSH SP
on an 8086 decrementsSP
before pushing it, whereas on a 286 it decrementsSP
after pushing it, so the value on the stack is different; - bus interactions (
LOCK
prefixes) behave differently on the 8086/8088 compared to all later CPUs; - illegal opcodes which run without error on the 8086 produce exceptions on later CPUs;
- the 8086 has no instruction length limit, whereas instructions which are too long will produce exceptions on later CPUs;
- segment wraparounds inside an instruction or word access work on the 8086 but trap on later CPUs;
- stack wraparounds work on the 8086 but will shut down a 286 or later;
- divide errors behave differently on the 8086/8088 compared to all later CPUs.
The 8086 also has a few bugs which were fixed in later CPUs, but that generally doesn’t matter — all it means is that the workarounds which were needed on 8086/8088 are no longer necessary on later CPUs. (One example is the handling of interrupted instructions with multiple prefixes.)
Software which is actually affected by differences other than speed is very rare indeed, and you can count on the vast majority of software still technically working on a modern x86 CPU in real mode. Speed is another matter; famously, programs written using Turbo Pascal fail with an “Error 200” on CPUs faster than a 200MHz Pentium, and many games don’t cope well with faster CPUs (but some CPUs can be slowed down in creative ways).
Great write up, except speed issues are not really due a changed/extended ISA - they would occure as well back then when speed up occured - after all, having a 10 MHz 8086 was already in the early 1980s a way to screw programs made for a 4.77 MHz 8088
– Raffzahn
Apr 5 at 21:13
The fact that it applies to 8MHz v. 4.77 MHz 8086s doesn’t mean it stops applying when comparing any other CPU to an 8086/8088 ;-).
– Stephen Kitt
Apr 5 at 21:15
2
Another difference between the 8086 and chips with protected mode: the 286+ didn't wrap around addresses at the 1MB mark in real mode, so IBM had to add an A20 line mask to work around that issue: although not generally an issue on PCs, it could theoretically happen if the A20 line has been enabled to access the UMB region and a program tried using wraparound to access low memory. It's pretty unlikely however: I've never seen a program crash in that manner!
– ErikF
Apr 5 at 23:00
3
@ErikF: ugh, A20 is an issue on modern PCs for everything except running legacy code, if you boot in legacy BIOS mode. But even that whole way of booting is obsoleted by UEFI, but that doesn't stop the majority of Stack Overflow "osdev" / "bootloader" questions being about legacy BIOS boot sectors. (Which start in real mode with A20 disabled, so it has to be manually enabled if you want to use odd 1MB regions of memory.) Of course, Intel themselves continue to support the undocumented 8086 SALC instruction in 32-bit mode... agner.org/optimize/blog/read.php?i=25
– Peter Cordes
Apr 6 at 3:29
1
Thanks @ErikF, that was indeed an issue (minor nitpick: accessing UMBs didn’t require A20 control, only the HMA did). Significant effort went into correctly handling the A20 line in memory managers...
– Stephen Kitt
Apr 6 at 17:05
|
show 3 more comments
An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example:
- newer CPUs run faster (in general);
- newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode);
- 286 and later CPUs add more address lines, and the wrapping behaviour of the 8086 meant that IBM had to add the infamous A20 gate to preserve backward-compatibility;
- instruction timing — the speed of individual CPU instructions — varies from one family to another; some instructions run more slowly on newer CPUs;
- implementation details vary, and in some cases, can affect run-time behaviour — for example, varying prefetch queue lengths mean that self-modifying code may not work on CPUs other than the model it was written for;
- some instructions behave differently — for example,
PUSH SP
on an 8086 decrementsSP
before pushing it, whereas on a 286 it decrementsSP
after pushing it, so the value on the stack is different; - bus interactions (
LOCK
prefixes) behave differently on the 8086/8088 compared to all later CPUs; - illegal opcodes which run without error on the 8086 produce exceptions on later CPUs;
- the 8086 has no instruction length limit, whereas instructions which are too long will produce exceptions on later CPUs;
- segment wraparounds inside an instruction or word access work on the 8086 but trap on later CPUs;
- stack wraparounds work on the 8086 but will shut down a 286 or later;
- divide errors behave differently on the 8086/8088 compared to all later CPUs.
The 8086 also has a few bugs which were fixed in later CPUs, but that generally doesn’t matter — all it means is that the workarounds which were needed on 8086/8088 are no longer necessary on later CPUs. (One example is the handling of interrupted instructions with multiple prefixes.)
Software which is actually affected by differences other than speed is very rare indeed, and you can count on the vast majority of software still technically working on a modern x86 CPU in real mode. Speed is another matter; famously, programs written using Turbo Pascal fail with an “Error 200” on CPUs faster than a 200MHz Pentium, and many games don’t cope well with faster CPUs (but some CPUs can be slowed down in creative ways).
An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example:
- newer CPUs run faster (in general);
- newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode);
- 286 and later CPUs add more address lines, and the wrapping behaviour of the 8086 meant that IBM had to add the infamous A20 gate to preserve backward-compatibility;
- instruction timing — the speed of individual CPU instructions — varies from one family to another; some instructions run more slowly on newer CPUs;
- implementation details vary, and in some cases, can affect run-time behaviour — for example, varying prefetch queue lengths mean that self-modifying code may not work on CPUs other than the model it was written for;
- some instructions behave differently — for example,
PUSH SP
on an 8086 decrementsSP
before pushing it, whereas on a 286 it decrementsSP
after pushing it, so the value on the stack is different; - bus interactions (
LOCK
prefixes) behave differently on the 8086/8088 compared to all later CPUs; - illegal opcodes which run without error on the 8086 produce exceptions on later CPUs;
- the 8086 has no instruction length limit, whereas instructions which are too long will produce exceptions on later CPUs;
- segment wraparounds inside an instruction or word access work on the 8086 but trap on later CPUs;
- stack wraparounds work on the 8086 but will shut down a 286 or later;
- divide errors behave differently on the 8086/8088 compared to all later CPUs.
The 8086 also has a few bugs which were fixed in later CPUs, but that generally doesn’t matter — all it means is that the workarounds which were needed on 8086/8088 are no longer necessary on later CPUs. (One example is the handling of interrupted instructions with multiple prefixes.)
Software which is actually affected by differences other than speed is very rare indeed, and you can count on the vast majority of software still technically working on a modern x86 CPU in real mode. Speed is another matter; famously, programs written using Turbo Pascal fail with an “Error 200” on CPUs faster than a 200MHz Pentium, and many games don’t cope well with faster CPUs (but some CPUs can be slowed down in creative ways).
edited Apr 8 at 9:41
Community♦
1
1
answered Apr 5 at 21:01
Stephen KittStephen Kitt
41.5k8170178
41.5k8170178
Great write up, except speed issues are not really due a changed/extended ISA - they would occure as well back then when speed up occured - after all, having a 10 MHz 8086 was already in the early 1980s a way to screw programs made for a 4.77 MHz 8088
– Raffzahn
Apr 5 at 21:13
The fact that it applies to 8MHz v. 4.77 MHz 8086s doesn’t mean it stops applying when comparing any other CPU to an 8086/8088 ;-).
– Stephen Kitt
Apr 5 at 21:15
2
Another difference between the 8086 and chips with protected mode: the 286+ didn't wrap around addresses at the 1MB mark in real mode, so IBM had to add an A20 line mask to work around that issue: although not generally an issue on PCs, it could theoretically happen if the A20 line has been enabled to access the UMB region and a program tried using wraparound to access low memory. It's pretty unlikely however: I've never seen a program crash in that manner!
– ErikF
Apr 5 at 23:00
3
@ErikF: ugh, A20 is an issue on modern PCs for everything except running legacy code, if you boot in legacy BIOS mode. But even that whole way of booting is obsoleted by UEFI, but that doesn't stop the majority of Stack Overflow "osdev" / "bootloader" questions being about legacy BIOS boot sectors. (Which start in real mode with A20 disabled, so it has to be manually enabled if you want to use odd 1MB regions of memory.) Of course, Intel themselves continue to support the undocumented 8086 SALC instruction in 32-bit mode... agner.org/optimize/blog/read.php?i=25
– Peter Cordes
Apr 6 at 3:29
1
Thanks @ErikF, that was indeed an issue (minor nitpick: accessing UMBs didn’t require A20 control, only the HMA did). Significant effort went into correctly handling the A20 line in memory managers...
– Stephen Kitt
Apr 6 at 17:05
|
show 3 more comments
Great write up, except speed issues are not really due a changed/extended ISA - they would occure as well back then when speed up occured - after all, having a 10 MHz 8086 was already in the early 1980s a way to screw programs made for a 4.77 MHz 8088
– Raffzahn
Apr 5 at 21:13
The fact that it applies to 8MHz v. 4.77 MHz 8086s doesn’t mean it stops applying when comparing any other CPU to an 8086/8088 ;-).
– Stephen Kitt
Apr 5 at 21:15
2
Another difference between the 8086 and chips with protected mode: the 286+ didn't wrap around addresses at the 1MB mark in real mode, so IBM had to add an A20 line mask to work around that issue: although not generally an issue on PCs, it could theoretically happen if the A20 line has been enabled to access the UMB region and a program tried using wraparound to access low memory. It's pretty unlikely however: I've never seen a program crash in that manner!
– ErikF
Apr 5 at 23:00
3
@ErikF: ugh, A20 is an issue on modern PCs for everything except running legacy code, if you boot in legacy BIOS mode. But even that whole way of booting is obsoleted by UEFI, but that doesn't stop the majority of Stack Overflow "osdev" / "bootloader" questions being about legacy BIOS boot sectors. (Which start in real mode with A20 disabled, so it has to be manually enabled if you want to use odd 1MB regions of memory.) Of course, Intel themselves continue to support the undocumented 8086 SALC instruction in 32-bit mode... agner.org/optimize/blog/read.php?i=25
– Peter Cordes
Apr 6 at 3:29
1
Thanks @ErikF, that was indeed an issue (minor nitpick: accessing UMBs didn’t require A20 control, only the HMA did). Significant effort went into correctly handling the A20 line in memory managers...
– Stephen Kitt
Apr 6 at 17:05
Great write up, except speed issues are not really due a changed/extended ISA - they would occure as well back then when speed up occured - after all, having a 10 MHz 8086 was already in the early 1980s a way to screw programs made for a 4.77 MHz 8088
– Raffzahn
Apr 5 at 21:13
Great write up, except speed issues are not really due a changed/extended ISA - they would occure as well back then when speed up occured - after all, having a 10 MHz 8086 was already in the early 1980s a way to screw programs made for a 4.77 MHz 8088
– Raffzahn
Apr 5 at 21:13
The fact that it applies to 8MHz v. 4.77 MHz 8086s doesn’t mean it stops applying when comparing any other CPU to an 8086/8088 ;-).
– Stephen Kitt
Apr 5 at 21:15
The fact that it applies to 8MHz v. 4.77 MHz 8086s doesn’t mean it stops applying when comparing any other CPU to an 8086/8088 ;-).
– Stephen Kitt
Apr 5 at 21:15
2
2
Another difference between the 8086 and chips with protected mode: the 286+ didn't wrap around addresses at the 1MB mark in real mode, so IBM had to add an A20 line mask to work around that issue: although not generally an issue on PCs, it could theoretically happen if the A20 line has been enabled to access the UMB region and a program tried using wraparound to access low memory. It's pretty unlikely however: I've never seen a program crash in that manner!
– ErikF
Apr 5 at 23:00
Another difference between the 8086 and chips with protected mode: the 286+ didn't wrap around addresses at the 1MB mark in real mode, so IBM had to add an A20 line mask to work around that issue: although not generally an issue on PCs, it could theoretically happen if the A20 line has been enabled to access the UMB region and a program tried using wraparound to access low memory. It's pretty unlikely however: I've never seen a program crash in that manner!
– ErikF
Apr 5 at 23:00
3
3
@ErikF: ugh, A20 is an issue on modern PCs for everything except running legacy code, if you boot in legacy BIOS mode. But even that whole way of booting is obsoleted by UEFI, but that doesn't stop the majority of Stack Overflow "osdev" / "bootloader" questions being about legacy BIOS boot sectors. (Which start in real mode with A20 disabled, so it has to be manually enabled if you want to use odd 1MB regions of memory.) Of course, Intel themselves continue to support the undocumented 8086 SALC instruction in 32-bit mode... agner.org/optimize/blog/read.php?i=25
– Peter Cordes
Apr 6 at 3:29
@ErikF: ugh, A20 is an issue on modern PCs for everything except running legacy code, if you boot in legacy BIOS mode. But even that whole way of booting is obsoleted by UEFI, but that doesn't stop the majority of Stack Overflow "osdev" / "bootloader" questions being about legacy BIOS boot sectors. (Which start in real mode with A20 disabled, so it has to be manually enabled if you want to use odd 1MB regions of memory.) Of course, Intel themselves continue to support the undocumented 8086 SALC instruction in 32-bit mode... agner.org/optimize/blog/read.php?i=25
– Peter Cordes
Apr 6 at 3:29
1
1
Thanks @ErikF, that was indeed an issue (minor nitpick: accessing UMBs didn’t require A20 control, only the HMA did). Significant effort went into correctly handling the A20 line in memory managers...
– Stephen Kitt
Apr 6 at 17:05
Thanks @ErikF, that was indeed an issue (minor nitpick: accessing UMBs didn’t require A20 control, only the HMA did). Significant effort went into correctly handling the A20 line in memory managers...
– Stephen Kitt
Apr 6 at 17:05
|
show 3 more comments
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)?
As so often it depends on your value of 'basically' (and there is no user visible difference between 8086 and 8088 beside speed).
Or are there differences between the two?
Well, it's so far the same, as every (modern) x86 operating in real mode will execute pure 8086 programs (*1) adhering to what were legal (*2) instructions (*3) on the 8086.
At the same time they are able to execute later extensions as well while in real mode. So it is possible to write 32-bit real mode programs, or use additional registers and instructions in real mode.
So a x86 isn't the same but for most parts (and depending on the CPU used) a compatible superset of an 8086.
*1 - Lets ignore 'external' hardware differences for this.
*2 - There are a few instructions that changed over time, including basic 8086 ones. They may cause incompatibilities in rare circumstances.
*3 - There are some non-instruction combinations (i.e. prefixes) that were ignored on 8086 but will throw interrupts on later CPUs or result in addressing errors. This is a classic case of later restrictions on less well defined behaviour (like double segment prefix and the like).
add a comment |
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)?
As so often it depends on your value of 'basically' (and there is no user visible difference between 8086 and 8088 beside speed).
Or are there differences between the two?
Well, it's so far the same, as every (modern) x86 operating in real mode will execute pure 8086 programs (*1) adhering to what were legal (*2) instructions (*3) on the 8086.
At the same time they are able to execute later extensions as well while in real mode. So it is possible to write 32-bit real mode programs, or use additional registers and instructions in real mode.
So a x86 isn't the same but for most parts (and depending on the CPU used) a compatible superset of an 8086.
*1 - Lets ignore 'external' hardware differences for this.
*2 - There are a few instructions that changed over time, including basic 8086 ones. They may cause incompatibilities in rare circumstances.
*3 - There are some non-instruction combinations (i.e. prefixes) that were ignored on 8086 but will throw interrupts on later CPUs or result in addressing errors. This is a classic case of later restrictions on less well defined behaviour (like double segment prefix and the like).
add a comment |
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)?
As so often it depends on your value of 'basically' (and there is no user visible difference between 8086 and 8088 beside speed).
Or are there differences between the two?
Well, it's so far the same, as every (modern) x86 operating in real mode will execute pure 8086 programs (*1) adhering to what were legal (*2) instructions (*3) on the 8086.
At the same time they are able to execute later extensions as well while in real mode. So it is possible to write 32-bit real mode programs, or use additional registers and instructions in real mode.
So a x86 isn't the same but for most parts (and depending on the CPU used) a compatible superset of an 8086.
*1 - Lets ignore 'external' hardware differences for this.
*2 - There are a few instructions that changed over time, including basic 8086 ones. They may cause incompatibilities in rare circumstances.
*3 - There are some non-instruction combinations (i.e. prefixes) that were ignored on 8086 but will throw interrupts on later CPUs or result in addressing errors. This is a classic case of later restrictions on less well defined behaviour (like double segment prefix and the like).
When an x86 CPU is running in real mode, can it be considered to be basically an 8086 CPU (or maybe 8088)?
As so often it depends on your value of 'basically' (and there is no user visible difference between 8086 and 8088 beside speed).
Or are there differences between the two?
Well, it's so far the same, as every (modern) x86 operating in real mode will execute pure 8086 programs (*1) adhering to what were legal (*2) instructions (*3) on the 8086.
At the same time they are able to execute later extensions as well while in real mode. So it is possible to write 32-bit real mode programs, or use additional registers and instructions in real mode.
So a x86 isn't the same but for most parts (and depending on the CPU used) a compatible superset of an 8086.
*1 - Lets ignore 'external' hardware differences for this.
*2 - There are a few instructions that changed over time, including basic 8086 ones. They may cause incompatibilities in rare circumstances.
*3 - There are some non-instruction combinations (i.e. prefixes) that were ignored on 8086 but will throw interrupts on later CPUs or result in addressing errors. This is a classic case of later restrictions on less well defined behaviour (like double segment prefix and the like).
edited Apr 5 at 23:11
answered Apr 5 at 21:02
RaffzahnRaffzahn
57.5k6140234
57.5k6140234
add a comment |
add a comment |
Thanks for contributing an answer to Retrocomputing Stack Exchange!
- Please be sure to answer the question. Provide details and share your research!
But avoid …
- Asking for help, clarification, or responding to other answers.
- Making statements based on opinion; back them up with references or personal experience.
To learn more, see our tips on writing great answers.
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
StackExchange.ready(
function ()
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fretrocomputing.stackexchange.com%2fquestions%2f9588%2fcan-an-x86-cpu-running-in-real-mode-be-considered-to-be-basically-an-8086-cpu%23new-answer', 'question_page');
);
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown